1. Field of the Invention
The present invention is generally directed to electronic design technologies for semiconductor products.
2. Description of the Related Art
For designing pipelined circuits, it may be required to design latency (the amount of delay) of each block to be the same among multiple blocks. The term “latency” here refers to a clock cycle number from when data reach the input of a block to when the data are transmitted to the output of the block.
Adjustment of such latency is explained with reference to FIG. 1. In FIG. 1, latency of Block A is “3” and latency of Block B is “2”. That is, in Block A, a change at an input AIN0 is output from an output AOUT0 in the third clock cycle due to the interposition of registers and, therefore, the latency is “3”. Combinational circuits have no effect on the latency. In a similar manner, in Block B, a change at an input BIN0 is output from an output BOUT0 in the second clock cycle and, therefore, the latency is “2”.
With such pipelined circuits, in some cases, the data arrival time (clock cycle time) needs to be the same between inputs CIN0 and CIN1 of Block C in FIG. 1. In the case of FIG. 1, since the latency of Block A is “3”, data arrive at the input CIN0 of Block C three clock cycles after the arrival of the data at the input AIN0 of Block A. On the other hand, since the latency of Block B is “2”, data arrive at the input CIN1 of Block C two clock cycles after the arrival of the data at the input BIN0 of Block B. Assume here that the data arrive at the input AIN0 of Block A and the input BIN0 of Block B at the same time.
In such conditions, the data arrival times at the inputs CIN0 and CIN1 of Block C are conventionally set to be the same in the following manner.
First, the data arrival times at the inputs CIN0 and CIN1 of Block C are visually checked based on logic simulation results, and the difference between the data arrival times is calculated manually.
Next, if there is a difference in the data arrival times, a register (flip-flop) or registers for latency adjustment are manually inserted into circuit data. FIG. 2 shows that a register DELAY_FF has been added to Block B.
Thus in the case of calculating the difference in the data arrival times and inserting a register/registers manually, if there are many data junctions, a point or points at which the data arrival times are not the same may fail to be noticed, or the difference in the data arrival times may be incorrectly calculated. As a result, the design efficiency decreases.
In order to solve such problems, Patent Document 1 discloses a technique for, by high-level synthesis, adjusting latency among multiple threads which operate concurrently.    [Patent Document 1] Japanese Patent No. 3763700
However, because of being based on high-level synthesis, the technique disclosed in Patent Document 1 is not applicable for adjusting latency between a block designed by high-level synthesis and a block designed by existing design technology which is not high-level synthesis. Also, the disclosed technique cannot be applied to a circuit composed only of blocks designed by existing design technology which is not high-level design technology.